Single instruction, single data (“SISD”) processing techniques and processors are common in graphics pipelines of most traditional graphics processing units (“GPUs”). SISD processing elements operate on single units of data at a time. Examples of such SISD processing elements include vertex and pixel processors (or shaders). SISD-compatible interfaces connect the various SISD processing elements to each other. For example, one type of SISD-compatible interface couples a traditional SISD-based vertex processor to a single data stream of vertex attributes. Once the SISD vertex processor receives the vertex attributes, it operates on the attributes in one thread of execution. While functional, conventional interfaces for SISD processing elements in graphics pipelines are not well suited for supporting processing elements that implement single instruction, multiple data (“SIMD”) processing techniques. Thus, graphics pipelines that provide vertex information in a single data stream cannot readily be adapted to support multi-threaded processing.
In view of the foregoing, it would be desirable to provide an apparatus, a method, a programmable GPU, a computer device, and a computer medium that minimize the above-mentioned drawbacks, thereby facilitating, among other functions, parallel processing in at least a portion of a programmable graphics pipeline, such as in a vertex processor.